- DCC Command Serialisation PIO module
This module contains the class and functions for low level DCC Command Serialisation for use with RailCom detection.
An RP2040 Peripheral Input Output (PIO) block is used to generate the DCC signal. A 'booster' is required to enable to track to be powered. One of the many DC motor H-bridge chips (e.g. DRV8874) should be suitable. The sleep pin puts the H-bridge into sleep mode when track power is not required. The enable pin is used for the RailCom cutout, putting both sides of the bridge into low impedance mode to ground and thereby creating the circuit required for the RailCom back channel.
A command comprises a preamble, one or more instruction/data bytes and an error detection (checksum) byte. Each byte is preceeded by a single '0' bit. The checksum is followed by a single '1' bit which may be the initial bit of the next preamble. The preamble is at least 14 '1' bits. Note that in this implementation the pre-amble is not interrupted by the cutout so the preamble length doesn't need to be lengthened but for compliance RCN-217 the pre-amble is set to 18 bits.
The DCC signal is a series of '1' & '0' bits. Each bit is encoded into a complete DCC output cycle. The half cycle length for a '1' is 58us, a '0' is 100us. The DCC output pin is set high for the first half cycle of a bit and low for second half cycle. The PIO FIFO buffer is 32 bits wide - 1 word. The RX FIFO is not used so is joined to the TX FIFO. This gives a total FIFO of 8 words. Each word holds two DCC command bytes plus framing bits.
If the FIFO is empty, the PIO doesn't stall but continues outputing '0' bits until the FIFO is loaded with a new command.
RCN-210 & RCN-211 partly apply as appropriate.
See also NMRA Standards S 9.2 and S 9.2.1. S 9.2.1.1 is not supported.
| Author | |
| Paul Redhead |